RC delay during charging and discharging is always dominant issue in signal propagation delay when driving large integrated circuits, such as for memory arrays of NAND, BICS or 3D type. Although the voltage transition can be applied to the circuit as an ideal step response, at the far end of the circuit the response will be dependent upon the time constant τ=RC of the circuit elements being driven. To reach within 99% of the final target level takes at least 4.6 τ. If RC time constant is large due to the R and C values of the driven component, then delay cannot be avoided. As the size and complexity of memory arrays and other circuit components continue to expand, there is a need for methods to improve such transition times in order to improve performance.